Description: Our Telecommunications Partner in Ottawa is seeking an ASIC Verification Engineer (UVM) to join thier growing R&D team.
This Verification Engineer position is your opportunity to join one of the industry’s leading companies in Smart Edge SoCs for network/systems control, management security systems, and IIoT.
Top Skills' Details
1.) SoC or ASIC Verification/Design
2.) UVM
3.) Digital Design
You should be familiar with UVM verification and the creation of UVM environments.
Working with industry-standard verification approaches including UVM, Portable Stimulus, and Formal verification procedures, you will be in charge of RTL SoC/Subsystem verification of ARM-based CPUs.
Day to Day:
Assistance with test plan conception and development, RTL and microarchitecture design validation, and documentation;
performance, power, and use-case verification at the top and block levels; and up until the point where production is mature, support test program development, chip validation, and chip life.
Working together with teams from the firmware, software, DV, FPGA, DFT, SoC integration, and backend during different stages of the ASIC development process.
Additional Qualifications & Skills
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L’entreprise souscrit au principe d’égalité d’accès à l’emploi et prendra en compte toutes les candidatures sans distinction de race, sexe, âge, couleur, religion, nationalité, statut de vétéran, handicap, orientation sexuelle, identité sexuelle, information génétique ou toute autre distinction protégée par la loi.
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The company is an equal opportunity employer and will consider all applications without regards to race, sex, age, color, religion, national origin, veteran status, disability, sexual orientation, gender identity, genetic information or any characteristic protected by law.
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